Sultanah Abdulrahman Almutairi

Artificial Intelligence Specialization · Cohort 2026

Systolic Arrays on a Heterogeneous MPSoC-FPGA Cluster

Deploying scientific computing workloads on a single FPGA often encounters severe memory and resource bottlenecks, limiting both performance and scalability. To address these constraints, this project explores a heterogeneous architecture based on a cluster of FPGA-based Multi-Processor System-on-Chip (MPSoC) devices to accelerate large-scale matrix multiplication using systolic arrays. The methodology emphasizes efficient workload partitioning across multiple heterogeneous nodes and systematically compares two communication paradigms: interconnection through the Processing System (PS) using a standard Ethernet stack, and ultra-low-latency hardware-level interconnection through the Programmable Logic (PL) using high-performance interfaces. The study will quantitatively evaluate how network topology affects bandwidth utilization, latency, and data starvation in distributed spatial computing environments. It will also investigate the distribution of computation across CPUs, GPUs, and FPGAs, analyzing the advantages and disadvantages of each architecture for scientific computing workloads. The results are expected to provide practical insights and design guidelines for efficiently scaling scientific computing workloads on FPGA clusters, improving throughput, energy efficiency, and real-time performance for large-scale matrix operations.

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